The present invention relates to Very Large Scale Integration (VLSI) circuits, and more specifically, to power grids of VLSI circuits.
VLSI circuits are comprised of many interconnected cells that perform one or more logic functions. For example, a VLSI circuit may be a collection of complementary metal-oxide-semiconductor (CMOS) circuits. Despite continued efforts to scale down circuit components and increase circuit densities, lack of voltage scaling beyond a certain level has led to higher current densities in metal interconnects. The increased current densities ultimately limit scalability because any space occupied by a current-carrying power supply wire can be thought of as space taken away for routing a signal wire.
One approach to addressing the increased current densities involves using a “sandwich structure” that duplicates power wires on vertically adjacent layers. However, this approach is limited to specific library cell images and to the first two metal layers, because it would be impractical to have a wrong-way (i.e., lengthwise perpendicular to most of the other wires) power grid on some of the levels of metal planes higher in the stack. Another approach is to widen power wires within only those cells that are expected to draw significant current through the supply wires. However, the library cells generally only have power pins on the first one or two metal levels. Thus, fixes (wider power wires) to the library cells do not affect power capacity at other levels or the need to design a higher level power grid that can service the worst-case expected current density. Further, even at the local cell level, power and ground buses are often shared at the cell boundaries. Thus, the power buses in the cells have to be wide enough to carry the current required for two high-powered cells, because two such cells may be placed next to each other. Also, the power actually consumed by a high-power cell depends on various factors such as the frequency at which the cell is being operated, the load it drives, etc. Thus, the local power connections in the cell have to be built to handle the worst-case application conditions, as well.
As the above discussion suggests, conventional approaches generally rely on “brute-force” techniques using a pre-planned uniform power grid to provide a robust solution for any conceivable combination of circuits that may be encountered in the VLSI design. This results in over-engineered power grids for much of the circuit design. The cost of providing this type of robust power grid design by the “brute-force” techniques is the unnecessary use of space for power grid wires that could otherwise have been used for signal wires. Thus, the worst-case approach to power grid design has limited the scalability of VLSI circuits. Consequently, a system and method of power grid design that addresses the trade-off between current density and signal wires and the issues presented by previous techniques would be appreciated in the integrated circuit design industry.